Programmable devices are a class of general-purpose integrated circuits that can be configured for a wide variety of applications. Such programmable devices have two basic versions, mask programmable devices, which are programmed only by a manufacturer, and field programmable devices, which are programmable by the end-user. In addition, programmable devices can be further categorized as programmable memory devices or programmable logic devices. Programmable memory devices include programmable ready-only memory (PROM), erasable programmable read-only memory (EPROM) and electronically erasable programmable read-only memory (EEPROM). Programmable logic devices include programmable logic array (PLA) devices, programmable array logic (PAL) devices, erasable programmable logic devices (EPLD), and programmable gate arrays (PGA).
Field programmable gate arrays (FPGA) have become very popular for telecommunication applications, Internet applications, switching applications, routing applications, et cetera. Generally, an FPGA includes a programmable logic fabric and a programmable input/output section. The programmable logic fabric may be programmed to perform a wide variety of functions corresponding to the particular end-user applications. The programmable logic fabric may be implemented in a variety of ways. For example, the programmable logic fabric may be implemented in a systematic array configuration, a row base configuration, a sea-of-gates configuration, or a hierarchical programmable logic device configuration.
The programmable input/output section may be fabricated on the perimeter of a substrate supporting the FPGA and provides coupling to the pins of the integrated circuit package allowing users access to the programmable logic fabric. Typically, the programmable input/output section includes a number of serial/deserial transceivers to provide access to the programmable logic fabric. Such transceivers include a receiver section that receives incoming serial data and converts it into parallel data and a transmitter section that converts outgoing parallel data into an outgoing serial data stream.
Since FPGA's are used in a wide variety of applications, which are typically governed by one or more standards, the transceivers need to be able to accommodate a wide variety of data. For example, data based standards, such as 10G Ethernet, Infiniband, Fibre Channel, have parallel input data widths in multiples of ten (e.g., 10 bits, 20 bits, 40 bits, etc.) while telecom based standards, such as SONET OC-48 and OC-192, have parallel input data widths in multiples of eight (e.g., 8 bits, 16 bits, 32 bits, 64 bits, etc.). To accommodate the different types of input parallel data, the receive path of the transceivers included two parallel to serial converters: one for each type of parallel input data. While this solution allows the FPGA to facilitate the wide variety of applications, it is costly in die area since effectively redundant circuits are included on the die and only one is used at a time.
Therefore, a need exists for a programmable serial data path that can accommodate input parallel data of varying data width multiples.